In recent years, as semiconductor integrated circuit devices have been miniaturized, a gap between wirings connecting devices or elements in a device has also been reduced. Therefore, a capacitance between wirings increases, leading to a decrease in signal propagation speed, which problem has come to the surface. Therefore, for example, a method of forming an air gap between wirings so as to reduce the capacitance has been proposed as described in Patent Document 1.
Hereinafter, a conventional method for fabricating a semiconductor device described in Patent Document 1 will be described with reference to the accompanying drawings.
FIGS. 18(a) to (d) and FIGS. 19(a) to (c) are cross-sectional views showing the conventional semiconductor device fabricating method in order in which the device is fabricated.
Initially, as shown in FIG. 18(a), a first insulating film 10 is deposited on a semiconductor substrate (not shown) on which a semiconductor active element is provided, and thereafter, recesses are formed in the first insulating film 10. Next, a first barrier metal film 11 is formed on bottom portions and wall portions of the recesses in the first insulating film 10, and thereafter, the recesses are filled with a copper film to form first wirings 12.
Next, as shown in FIG. 18(b), a liner insulating film 13 is deposited on the first insulating film 10 and the first wirings 12 so as to prevent the first wirings 12 from peeling off and prevent copper included in the first wirings 12 from diffusing.
Next, as shown in FIG. 18(c), a resist pattern 14 is formed on the liner insulating film 13 by lithography. The resist pattern 14 has an opening pattern 14a which allows removal of only portions between desired first wirings 12 in the first insulating film 10, and is used so as to form inter-wiring gaps between the desired first wirings 12. In other words, the resist pattern 14 is a mask pattern which exposes only regions between the desired first wirings 12.
Next, as shown in FIG. 18(d), the liner insulating film 13 and the first insulating film 10 are subjected to dry etching using the resist pattern 14 as a mask, to form inter-wiring gaps 15 between the first wirings 12.
Next, as shown in FIG. 19(a), a second insulating film 17 is deposited on the inter-wiring gaps 15 between the first wirings 12 and the liner insulating film 13 to form air gaps 16 between the first wirings 12. A top portion of each air gap 16 protrudes above the liner insulating film 13. If a film which has a low coverage rate and poor filling performance is used as the second insulating film 17, the air gaps 16 can be easily formed.
Next, as shown in FIG. 19(b), a connection hole 17a which exposes a surface of a first wiring 12 is formed in the second insulating film 17 by etching, and thereafter, wiring trenches 17b are formed. In this case, Dual Damascene is employed in which the connection hole 17a is formed prior to the wiring trenches 17b. 
Next, as shown in FIG. 19(c), a barrier metal film is formed on the second insulating film 17 including the connection hole 17a and the wiring trenches 17b, and thereafter, a plating film is formed using a seed film. Thereafter, excess portions of the barrier metal film, the seed film and the plating film extending off the insides of the connection hole 17a and the wiring trenches 17b are removed by metal CMP. As a result, a barrier metal film 18 and a via hole 19 are formed in the connection hole 17a, and a barrier metal film 20 and a second wiring 21 are formed in each wiring trench 17b. Thus, a double-layer wiring including the first wirings 12 and the second wirings 21 is formed.
Thus, a semiconductor device having a multilayer wiring, in which the air gap 16 is formed between the first wirings 12 made of a copper film, can be fabricated. The relative dielectric constant of the air gap 16 made of air is about ¼ of that of the first insulating film 10. Therefore, by providing the air gap 16, a capacitance between adjacent first wirings 12 can be reduced. Therefore, a signal delay between adjacent first wirings 12 can be suppressed, whereby a semiconductor device which has a large margin of operation and is less likely to malfunction can be achieved. Moreover, a conventional material for wirings can be utilized, leading to lower cost.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-120988